1 of 10 091399 features dual fixed frequency outputs (30 khz - 100 mhz) no external components 0.5% initial tolerance 1% variation over temperature and voltage single 5v supply power-down mode synchronous output gating description the ds1075 custom is a fixed frequency oscillator requiring no external components for operation. numerous operating frequencies are possible in the range 29.2 khz to 100 mhz through the use of an on- chip factory-programmable prescaler and divider. the ds1075 custom is shipped from the factory pre-programmed on a custom basis to the customers specified output frequency and mode of operation. the part is branded according to the device?s master frequency (see ds1075 data sheet). the customer fills out a ?1075 custom order form? with the required information and submits it to the factory for approval. custom econoscillators are available in two versions, simple custom and complex custom, that can be programmed at the factory in sample and volume quantities. simple custom parts are based on one of the standard master frequencies of 60, 66, 80 and 100 mhz with non-standard values programmed for the dividers and function select bits. an impressive number (over 1500) of sub-frequencies can be programmed using a simple custom part. complex custom parts have a non-standard master frequency (within the 60 mhz to 110 mhz range) programmed into the internal master oscillator and non-standard values are programmed for the dividers and function select bits. virtually any frequency within the 29.24 khz to 110 mhz range is possible using complex custom parts contact the factory for custom part selection and ordering information. the ds1075 custom is available in 8-pin dip or soic packages, allowing the generation of a clock signal easily, economically and using minimal board area. ds1075 custom econoscillator/divider preliminary www.dalsemi.com ds1075z 150-mil soic ds1075m 300-mil dip out1 out0 v cc gnd nc nc oe pdn 1 2 3 8 7 6 5 4
ds1075 2 of 10 block diagram figure 1 master oscillator 60-110mhz power down control divider divide by n 1-513 prescaler divide by m 1, 2, 4 out0 (optional) (reference) out1 oe pdn
ds1075 3 of 10 1075 custom order form use this form for ds1075 custom programmed econoscillators . all sections must be completed. refer to the datasheet or contact bob brown at (972) 371-3719 for assistance. parent part number: ds1075 customer name: ________________________________ _______________________________ customer contact: ________________________________ _____________________________ customer address: ________________________________ _____________________________ ________________________________ ________________________________ _____________ customer phone: (area) _____ _____ ________ salesman: ________________________________ ________________________________ ____ sales representative: ________________________________ ___________________________ distributor (if any): ________________________________ ____________________________ package: 300mil 8-pin dip 150mil 8-pin soic (circle one) parent device: ds ________________ ( part will be branded with this speed) master frequency: _________ mhz standard or custom (circle one) (60,66,80 or 100mhz) reference output: disabled enabled - frequency _________ (equals master frequency/m) output frequency: _________ (equals master frequency/mn) prescaler (m) : _________ divider (n): _________ special instructions (tape & reel, etc.): ________________________________ ________________________________ _____________ ________________________________ ________________________________ _____________ ________________________________ ________________________________ _____________ ________________________________ ________________________________ _____________ ________________________________ ________________________________ _____________ customer signature: _____________________________________ (acknowledges acceptance of custom settings) fax the completed form to bob brown at (972) 371-3717
ds1075 4 of 10 pin descriptions output pin (out1 pin): this pin is the main oscillator output, with a frequency determined by clock reference, m and n dividers. output enable function (oe pin): the ds1075 custom features a ?synchronous? output enable. when oe is at a high logic level the oscillator free runs. when this pin is taken low out/ is held low, immediately if out/ is already low, or at the next high-to-low transition if out/ is high. this prevents any possible truncation of the output pulse width when the enable is used. while the output is disabled the master oscillator continues to run (producing an output at out0, if the en0 bit = 0) but the internal counters (/n) are reset. this results in a constant phase relationship between oe?s return to a high level and the resulting out/ signal. when the enable is released out/ will make its first transition within one to two clock periods of the master clock. power-down ( pdn pin): a low logic level on this pin can be used to make the device stop oscillating (active low) and go into a reduced power consumption state. internal ?enabling sequencer? circuitry will first disable out in the same way as when oe is used. next out0 will be disabled in a similar fashion. finally the oscillator circuitry will be disabled. in this mode both outputs will go into a high impedance state. the power consumption in the power-down state is much less than if oe is used because the internal oscillator is completely powered down. consequently the device will take considerably longer to recover (i.e., achieve stable oscillation) from a power-down condition than if the oe is used. reference output (out0 pin): a reference output, out0, is also available from the output of the prescaler. out0 is unaffected by the oe pin, but is disabled in a glitchless fashion if the device is powered down. if this output is not required it can be permanently disabled and there will be a corresponding reduction in overall power consumption. the availability of this output and its frequency are specified on the custom order form. operation of output enable since the output enable and internal master oscillator are asynchronous there is the possibility of timing difficulties in the application. to minimize these difficulties the ds1075 features an ?enabling sequencer? to produce predictable results when the device is enabled and disabled. in particular the output gating is configured so that truncated output pulses can never be produced. enable timing the output enable function is produced by sampling the oe input with the output from the pre-scaler mux (mclk) and gating this with the output from the programmable divider. the exact behavior of the device is therefore dependent on the setup time (t su ) from a transition on the oe input to the rising edge of mclk. if the actual setup time is less than t suem then one more complete cycle of mclk will be required to complete the enable or disable operation (see diagrams). this is unlikely to be of any consequence in most applications, and then only if the value for n is small. in general, the output will make its first positive transition between approximately one and two clock periods of mclk after the rising edge of oe. (figure 2)
ds1075 5 of 10 figure 2 disable timing if oe goes low while out1 is high, the output will be disabled on the completion of the output pulse. if out1 is low, the disabling behavior will be dependent on the setup time between the falling edge of oe and the rising edge of mclk. if t su < t suem the result will be one additional pulse appearing on the output before disabling occurs. if the device is in divide-by-one mode, the disabling occurs slightly differently. in this case if t s > t suem one additional output pulse will appear, if t su < t suem then two additional output pulses will appear. the following diagrams illustrate the timing in each of these cases. (figure 3 and 4) figure 3 figure 4
ds1075 6 of 10 power-down control power-down if pdn is taken low a power-down sequence is initiated. the ?enabling sequencer? is used to execute events in the following sequence: 1. disable out1 (same sequence as when oe is used) and reset n counters. 2. when out1 is low, switch out1 to high-impedance state. 3. disable mclk, switch out0 to high impedance state. 4. disable master oscillator. power-up when pdn is taken to a high level the following power-up sequence occurs: 1. enable internal oscillator. 2. set m and n to maximum values. 3. wait approximately 256 cycles of mclk for it to stabilize. 4. reset m and n to programmed values. 5. enable out0 ( if enabled) 6. enable out1. steps 2 through 4 exist to allow the oscillator to stabilize before enabling the outputs. figure 5
ds1075 7 of 10 power-on reset when power is initially applied to the device supply pin, a power-on reset sequence is executed, similar to that which occurs when the device is restored from a power-down condition. this sequence comprises two stages, first a conventional por to initialize all on-chip circuitry, followed by a stabilization period to allow the oscillator to reach a stable frequency before enabling the outputs: 1. initialize internal circuitry. 2. enable internal oscillator. 3. set m and n to maximum values. 4. wait approximately 256 cycles of mclk for the oscillator to stabilize. 5. load m and n programmed values from eeprom. 6. enable out0 (if enabled). 7. enable out1. figure 6
ds1075 8 of 10 absolute maximum ratings* voltage on any pin relative to ground -1.0v to +7.0v operating temperature 0c to 70c storage temperature -55c to +125c soldering temperature 260c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (t a =0oc to 70oc; v cc = 5v 5%) parameter symbol condition min typ max units notes supply voltage v cc 4.75 5 5.25 v high-level output voltage (out1, out0) v oh i oh =-4 ma, v cc = min 2.4 v low-level output voltage (out1, out0) v ol i ol =4 ma 0.4 v high-level input voltage ( pdn , oe) v ih v ih 2 3 v v low-level input voltage ( pdn , oe) v il v il 0.8 2 v v high-level input current ( pdn , oe) i ih i ih v ih =2.4v, v cc =5.25v v ih =v cc =5.25v 1 25 a a low-level input current ( pdn , oe) i il i il v il =0, v cc =5.25v v il =0,v cc = 5.25v -1 -25 a a supply current (active) ds1075-100 ds1075-80 ds1075-66 ds1075-60 i cc c l =15pf (both outputs) v cc =5.25v 50 ma standby current i ccq power-down mode 0.8 a
ds1075 9 of 10 ac electrical characteristics (t a =0oc to 70oc; v cc = 5v 5%) parameter symbol condition min typ max units notes output frequency tolerance ?f o v cc =5v, t a =25 c -0.5 0 +0.5 % combined freq. variation ?f o over temp and voltage -1 +1 % long term stability ?f o -0.5 +0.5 % minimum output frequency f out master = 60mhz m=4, n-513 29.24 khz power-up time t por +t stab 0.1 1 ms 1, 2 enable out1 from pdn - t stab 0.1 1 ms 2 enable out0 from pdn - t stab 0.1 1 ms 2, 3 out1 hi-z from pdn t pdn 1 ms out0 hi-z from pdn t pdn 1 ms load capacitance (out1, out0) c l 15 pf 4 output duty cycle out1 out0 40 60 % notes: 1. this is the time from when v cc is applied until the output starts oscillating 2. when the device is initially powered up, or restored from the power-down mode, oe should be asserted (high).otherwise the start of the t stab interval will be delayed until oe goes high. oe can subsequently be returned to a low level during the t stab interval to force out low after the t stab interval. 3. although oe does not normally affect out0 operation, if oe is held low during power-up the start of the t stab period will be delayed until oe is asserted. if oe remains low, out0 will not start. 4. operation with higher capacitive loads is possible but may impair output voltage swing and maximum operation frequency .
ds1075 10 of 10 ac electrical characteristics -calculated parameters the following characteristics are derived from various device operating parameters (frequency, mode etc.). they are not specifically tested or guaranteed and may differ from the min and max limits shown by a small amount due to internal device setup times and propagation delays. however, these equations can be used to derive a more accurate idea of typical device performance than the guaranteed values. parameter symbol condition min max out1 - from oe - t en t m 2t m out1 from oe n =1 n = 2 t dis t dis t outh 0 t outh + t m t outh pdn to out1 hi-z n =1 n = 2 t pdn t pdn t outh 0 t outh + t m t outh pdn to out0 hi-z n =1 n = 2 t pdn t pdn t outh 0 t outh + t m t outh pdn - to out1 - t stab 256t m pdn - to out0 - t stab 256t m out1 - after power-up 256t m out0 - after power-up 256t m
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